1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a structure of a read/write control unit in a static random access memory.
2. Description of the Prior Art
Since a static random access memory requires a constant current to flow therethrough in contrast to a dynamic random access memory, it consumes a large amount of electric power. However, it requires no refreshing operations and can be operated at a high speed.
As is well known, a static random access memory formed of semiconductors includes generally a plurality of memory cells, each of which consists of a one-bit-signal memorizing flip-flop, are arranged like row and column matrixes; word lines connected to each row of the memory cells for the purpose of selecting a specific memory cell from the same memory cells, and bit lines connected to each column of the memory cells; a bit data line for connecting each column of the memory cells to a power source and a common data line; a write control circuit for writing data in the memory cells; and a read control circuit for reading data from the memory cells.
In order to form such a random access memory of semiconductor devices, such as MOS transistors, it is necessary to reduce the power dissipation.
There is a known method of reducing the power dissipation of such a static random access memory, in which an electric current flowing through a load MOS transistor on a bit data line between the memory cells and a power source is controlled (Japanese Patent Laid-open No. 132589/1980). This method consists of stopping the electric currents, which flow through the bit lines for the columns other than a selected column, by turning on and off by a column selecting signal such a load MOS transistor as mentioned above, so as to minimize the power dissipation of the memory.
However, when this method is used, an unnecessary constant current flows from a power source toward a data input circuit through a MOS transistor on a bit data line in a selected column during the write-in time, though a direct current does not flow into non-selected memory cells during the read-out time.
When this method is used, a difference between the electric potentials in two bit data lines at both sides of a memory cell in a non-selected column becomes several times as high as that in the case where a load MOS transistor is not turned off. Consequently when a selected word line is switched, incorrect turn-on or turn-off of the memory cell occurs.
For example, when the load MOS transistor is not turned off, both of the voltages in the two bit data lines during the read-out time are maintained at substantially the same level (about 3 V if the power source voltage is 5 V). On the other hand, when the load MOS transistor on the bit data line is turned off, the voltages in two bit data lines on the high level "H" side and low level "L" side of the memory cell differ greatly; when the power source voltage is 5 V, the voltage in the bit data line on the high level side becomes about 4 V, and the voltage in the bit data line on the low level side 0-1 V. If another word line is then selected with this load MOS transistor turned off, and if another column selecting signal is inputted at this time, a problem will occur. Namely, when the contents of a memory cell connected to these bit data lines and selected word line are contrary to those of the above-mentioned memory cell, the contents of the memory cell connected to the selected word line are written in the turned-over state due to the large difference between the voltages in the bit data lines.